This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these attacks. We demonstrate that recent reconfigurable devices offer excellent opportunities to implement a masked DES. In particular, we use the large embedded memories available in the Xilinx Virtex-II pro reg FPGAs to store precomputed and masked substitution tables. Compared to an unprotected DES design, our proposal only requires 45% more logic resources and 128 Kbit of memory and yields a throughput of about 1 Gbit/sec.
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机译：本文介绍了DES和Triple-DES的FPGA实现，具有针对功耗分析攻击的改进的安全性。拟议的设计使用布尔掩码，布尔掩码是一种以前介绍的技术，可以保护智能卡实现免受这些攻击。我们证明了最近的可重新配置设备为实施掩蔽DES提供了绝佳的机会。特别是，我们使用Xilinx Virtex-II pro reg FPGA中可用的大型嵌入式存储器来存储预先计算和掩码的替换表。与无保护的DES设计相比，我们的建议仅需要增加45％的逻辑资源和128 Kbit的内存，并产生大约1 Gbit / sec的吞吐量。
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